✦ LIBER ✦

Design and characterization of NULL convention arithmetic logic units

✍ Scribed by Satish K. Bandapati; Scott C. Smith

Book ID: 104050599
Publisher: Elsevier Science
Year: 2007
Tongue: English
Weight: 176 KB
Volume: 84
Category: Article
ISSN: 0167-9317
DOI: 10.1016/j.mee.2006.02.012

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design for Test of Asynchronous NULL Con

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

✍ Waleed K. Al-Assadi; Sindhu Kakarla 📂 Article 📅 2008 🏛 Springer US 🌐 English ⚖ 294 KB

Design and Evaluation of Adiabatic Arith

Design and Evaluation of Adiabatic Arithmetic Units

✍ Micah C. Knapp; Peter J. Kindlmann; Marios C. Papaefthymiou 📂 Article 📅 1997 🏛 Springer 🌐 English ⚖ 126 KB

Arithmetical logical unit design for a p

Arithmetical logical unit design for a processor with BILBO techniques: Functional simulation and test strategies

✍ M. Martinez; N.P. Cagigal; S. Bracho 📂 Article 📅 1990 🏛 Elsevier Science ⚖ 555 KB

Design and simulation of logic circuits

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature

✍ A. Venkataratnam; A.K. Goel 📂 Article 📅 2008 🏛 Elsevier Science 🌐 English ⚖ 568 KB

Design of a WSI scale parallel processor

Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units

✍ Yoshichika Fujioka; Nobuhiro Tomabechi 📂 Article 📅 2000 🏛 John Wiley and Sons 🌐 English ⚖ 254 KB 👁 1 views

A restructurable (reconfigurable) parallel VLSI processor designed to minimize the operation delay time which can be generally used for various operations necessary for controlling an intelligent robot was proposed previously by the authors. This processor is constructed by connecting a number of pr