Corrections to “Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs” [Oct 11 3379-3387]

✍ Scribed by Zou, J.; Xu, Q.; Luo, J.; Wang, R.; Huang, R.; Wang, Y.

• Book ID: 114620831
• Publisher: IEEE
• Year: 2012
• Tongue: English
• Weight: 86 KB
• Volume: 59
• Category: Article
• ISSN: 0018-9383
• DOI: 10.1109/ted.2011.2178417