✦ LIBER ✦

Control function margin degradation in a bubble memory chip

✍ Scribed by Yamaguchi, N.

Book ID: 119818926
Publisher: IEEE
Year: 1978
Tongue: English
Weight: 252 KB
Volume: 14
Category: Article
ISSN: 0018-9464
DOI: 10.1109/tmag.1978.1059736

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Temperature Dependence of Operating Marg

Temperature Dependence of Operating Margins for a 16-Mbit Bubble Memory Chip

✍ Ohashi, M.; Amatsu, M.; Nakagawa, Y.; Inoue, H. 📂 Article 📅 1988 🏛 Institute of Electrical and Electronics Engineers ⚖ 171 KB

Pinnacle: IBM MXT in a memory controller

Pinnacle: IBM MXT in a memory controller chip

✍ Tremaine, R.B.; Smith, T.B.; Wazlowski, M.; Har, D.; Kwok-Ken Mak; Arramreddy, S 📂 Article 📅 2001 🏛 IEEE 🌐 English ⚖ 184 KB

Bubble propagation and state control in

Bubble propagation and state control in the access column of a current accessed bubble lattice chip

✍ Chapman, D. 📂 Article 📅 1979 🏛 IEEE 🌐 English ⚖ 699 KB

Cognitive control functions in memory-im

Cognitive control functions in memory-impaired subjects: A neuropharmacological model

✍ H. Weingartner; K. Sirocco; M. Eckardt; D. Hommer; D.N. Johnson 📂 Article 📅 1994 🏛 Elsevier Science 🌐 English ⚖ 167 KB

Bias field margin degradation due to lon

Bias field margin degradation due to long-term memory operation in 16kbit bubble memory chips: N. Yamaguchi Proceedings of the 8th Conference (1976 International) on Solid State Devices, Tokyo, 1976; Japanese Journal of Applied Physics, 16, Supplement 16-1, pp.334–350 (1977)

📂 Article 📅 1979 🏛 Elsevier Science 🌐 English ⚖ 136 KB

Control mechanisms in working memory: A

Control mechanisms in working memory: A possible function of EEG theta oscillations

✍ Paul Sauseng; Birgit Griesmayr; Roman Freunberger; Wolfgang Klimesch 📂 Article 📅 2010 🏛 Elsevier Science 🌐 English ⚖ 408 KB

Neural correlates of control mechanisms in human working memory are discussed at two levels in this review: (i) at 'item level', where in multi-item working memory information needs to be organized into sequential memory representations, and (ii) at a 'process level', indicating the integration and