✦ LIBER ✦

Comments on "The Error Latency of a Fault in a Sequential Digital Circuit"

✍ Scribed by David, R.; Tellez-Giron, R.

Book ID: 114606218
Publisher: IEEE
Year: 1979
Tongue: English
Weight: 343 KB
Volume: C-28
Category: Article
ISSN: 0018-9340
DOI: 10.1109/tc.1979.1675230

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A method for reducing the target fault l

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

✍ Takahashi, H.; Keller, K.J.; Le, K.T.; Saluja, K.K.; Takamatsu, Y. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 524 KB

A metric for estimating the fault-secure

A metric for estimating the fault-secure behavior of digital circuits

✍ McNamer, M.; Kanopoulos, N. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 762 KB

Evaluation of a fan out stem based fault

Evaluation of a fan out stem based fault simulation in sequential circuits

✍ Frederick J. Hill; Eltayeb S. Abuelyaman 📂 Article 📅 1990 🏛 Elsevier Science 🌐 English ⚖ 547 KB

Design of a novel fault-tolerant voter c

Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

✍ R.V. Kshirsagar; R.M. Patrikar 📂 Article 📅 2009 🏛 Elsevier Science 🌐 English ⚖ 386 KB

Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, interference from radiation and noise-related transient faults. Many of these faults are not permanent in nature but their occurrence can result

Comments on "Fault Trees - A State of th

Comments on "Fault Trees - A State of the Art Discussion

✍ Yellman, Ted W. 📂 Article 📅 1975 🏛 IEEE 🌐 English ⚖ 840 KB

A Circuit for Concurrent Detection of So

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

✍ S. Matakias; Y. Tsiatouhas; A. Arapoyanni; Th. Haniotakis 📂 Article 📅 2004 🏛 Springer US 🌐 English ⚖ 682 KB