✦ LIBER ✦

Comments on "High-speed area-efficient multiplier design using multiple-valued current-mode circuits"

✍ Scribed by Parhami, B.; Kawahito, S.; Ishida, M.; Nakamura, T.; Kameyama, M.; Higuchi, T.

Book ID: 119772492
Publisher: IEEE
Year: 1996
Tongue: English
Weight: 231 KB
Volume: 45
Category: Article
ISSN: 0018-9340
DOI: 10.1109/12.509918

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

High-speed area-efficient multiplier des

High-speed area-efficient multiplier design using multiple-valued current-mode circuits

✍ Kawahito, S.; Ishida, M.; Nakamura, T.; Kameyama, M.; Higuchi, T. 📂 Article 📅 1994 🏛 IEEE 🌐 English ⚖ 884 KB

Use of multiple-valued logic with 1.9-V

Use of multiple-valued logic with 1.9-V operational power supply to obtain a high-speed current-mode logic circuit

✍ Yasuhiro Sugimoto 📂 Article 📅 1996 🏛 John Wiley and Sons 🌐 English ⚖ 635 KB

This paper proposes a new construction of bipolar current-mode (CML) logic circuits based on the multiple-valued logic concept. Applying the multiple-valued logic concept, the new logic function, which can replace the conventional stack logic circuit and can be operated by a low supply voltage, can

[IEEE 2009 European Conference on Circui

[IEEE 2009 European Conference on Circuit Theory and Design (ECCTD 2009) - Antalya, Turkey (2009.08.23-2009.08.27)] 2009 European Conference on Circuit Theory and Design - An area-speed efficient method for current mode analog to digital converters

✍ Khodabndehloo, Golnar; Mirhassani, Mitra; Ahmadi, Majid 📂 Article 📅 2009 🏛 IEEE ⚖ 589 KB