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Coherence controller architectures for scalable shared-memory multiprocessors

โœ Scribed by Michael, M.M.; Nanda, A.K.; Beng-Hong Lim


Book ID
119772959
Publisher
IEEE
Year
1999
Tongue
English
Weight
858 KB
Volume
48
Category
Article
ISSN
0018-9340

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Scalability of a multiprocessor architecture depends on its ability to manage interconnection network latency with increasing number of processors. Interconnection network latency can be minimized by reducing the distance traversed by a message in terms of number of nodes and wire lengths. Scalabili