✦ LIBER ✦

Challenges in the design high-speed clock and data recovery circuits

✍ Scribed by Razavi, B.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design of high-speed clock and data reco

✍ Tan Kok-Siang; Mohd-Shahiman Sulaiman; Chuah Hean-Teik; Manoj Sachdev 📂 Article 📅 2007 🏛 Springer 🌐 English ⚖ 425 KB

A burst mode all-digital high-speed cloc

✍ Yoichi Matsumoto; Masahiro Morikura; Shuzo Kato 📂 Article 📅 1993 🏛 John Wiley and Sons 🌐 English ⚖ 756 KB

A power and area efficient CMOS clock/da

✍ Dao-Long Chen 📂 Article 📅 1996 🏛 IEEE 🌐 English ⚖ 982 KB

Clock- and Data-Recovery Circuit With In

✍ Jun-Yong Song; Oh-Kyong Kwon 📂 Article 📅 2011 🏛 Institute of Electrical and Electronics Engineers 🌐 English ⚖ 741 KB

Timing and data recovery circuit for hig

✍ Luo, Y.-B.; Chiueh, T.-D. 📂 Article 📅 2003 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 459 KB

Design and performance of clock recovery

✍ Imai, Y.; Sano, E.; Nakamura, M.; Ishihara, N.; Kikuchi, H.; Ono, T. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 611 KB