Challenges for signal integrity prediction in the next decade

✍ Scribed by Xavier Aragones; Antonio Rubio

• Publisher: Elsevier Science
• Year: 2003
• Tongue: English
• Weight: 443 KB
• Volume: 6
• Category: Article
• ISSN: 1369-8001
• DOI: 10.1016/s1369-8001(03)00077-5

✦ Synopsis

Noise caused by the activity of integrated circuits is a limiting factor for the development of future VLSI circuits. Transients of voltages and currents couple perturbations to the co-integrated circuits where the most effective medium to propagate noise is the silicon substrate. The effect is especially important where high-speed digital circuits are integrated together with highly sensitive analog sections, which is the case of modern communication transceivers. Taking into account the effect of noise during the circuit design requires a fine electrical modeling of the substrate and noise generation. The capability of substrate to propagate signals from DC to very high frequencies has to be understood and modeled, together with the role of doping profile and topology of doped regions (layout). In this tutorial paper the sources, propagation of noise and sensitivity of MOS circuits are presented and its trend in the next technology generations is evaluated. The challenges that modeling techniques and CAD tools have to face are commented, and the key points and more likely solutions are discussed.