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Cadnetix launches physical modelling system for VLSI circuits


Book ID
104110450
Publisher
Elsevier Science
Year
1986
Tongue
English
Weight
95 KB
Volume
18
Category
Article
ISSN
0010-4485

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Delay fault models for VLSI circuits
โœ Irith Pomeranz; Sudhakar M Reddy ๐Ÿ“‚ Article ๐Ÿ“… 1998 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 218 KB

State-of-the-art technologies for VLSI circuits give rise to various defect mechanisms that may cause a circuit to fail when operated at its designated speed of operation. Such defects are conventionally modeled by delay faults. In this paper, we review delay fault models used for circuits described