This paper presents a conceptual model of burn-in decision making which gives an optimal burn-in time for semiconductor devices and describes how burn-in affects total yield and reliability. For the gate oxide of integrated circuits we consider four burn-in policies: no burn-in, wafer-level burn-in
Bounds to optimal burn-in and optimal work size
β Scribed by Ji Hwan Cha; Jie Mi
- Publisher
- John Wiley and Sons
- Year
- 2005
- Tongue
- English
- Weight
- 146 KB
- Volume
- 21
- Category
- Article
- ISSN
- 1524-1904
- DOI
- 10.1002/asmb.550
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