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Bit commitment using pseudo-random synthesizer

โœ Scribed by Dong Zheng; Shengli Liu; Yumin Wang


Book ID
107504337
Publisher
SP Science Press
Year
1999
Tongue
English
Weight
227 KB
Volume
16
Category
Article
ISSN
0217-9822

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A linear systolic array of 256 cells for computing the Goldbach partitions has been designed and implemented on the FPGA PeRLe-1 platform. Fast computation is achieved using a counter based on a pseudo-random bit generator. Beyond this application we show that FPGA technology tends to promote such a