BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
โ Scribed by Walter, I.; Cidon, I.; Kolodny, A.
- Book ID
- 114572061
- Publisher
- IEEE
- Year
- 2008
- Tongue
- English
- Weight
- 138 KB
- Volume
- 7
- Category
- Article
- ISSN
- 1556-6056
No coin nor oath required. For personal study only.
๐ SIMILAR VOLUMES
This paper presents a high level power estimation methodology for a Network-on-Chip (NoC) router, that is capable of providing cycle accurate power profile to enable power exploration at system level. Our power macro model is based on the number of flits passing through a router as the unit of abstr
This paper proposes a bus-based cube-type network, called psi-cube, that alleviates the two problems, long wires and a limited number of I/O pins, against the on-chip systems through a small diameter and dynamic clusters, respectively. The 2 n -node psi-cube is organized on the sets of node-partitio