๐”– Bobbio Scriptorium
โœฆ   LIBER   โœฆ

Automatic generation of tree level helicity amplitudes

โœ Scribed by T. Stelzer; W.F. Long

Publisher
Elsevier Science
Year
1994
Tongue
English
Weight
867 KB
Volume
81
Category
Article
ISSN
0010-4655

No coin nor oath required. For personal study only.

โœฆ Synopsis

The program MadGraph is presented which automatically generates postscript Feynman diagrams and Fortran code to calculate arbitrary tree level helicity amplitudes by calling HELAS [I] subroutines. The program is written in Fortran and is available in Unix and VMS versions. MadGraph currently includes standard model interactions of QCD and QFD, but is easily modified to include additional models such as supersymmetry.

๐Ÿ“œ SIMILAR VOLUMES

Automatic generation of Feynman graphs a
Automatic generation of Feynman graphs and amplitudes in QED
โœ T. Kaneko; S. Kawabata; Y. Shimizu ๐Ÿ“‚ Article ๐Ÿ“… 1987 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 842 KB

Operating system: OSIV/F4 MSP (FACOM), VOS3 (HITAC), ## VMS(VAX) Programming language used: PASCAL High speed storage required: 160 Kwords (depending on the physical reaction) No. of bits in a word: 32 Peripherals used: terminal or card reader for input, magnetic disk, line printer and graphic d

Automatic generation of command level si
Automatic generation of command level simulation model of a processor from rt level description
โœ Hiroki Akaboshi; Hiroto Yasuura ๐Ÿ“‚ Article ๐Ÿ“… 1996 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 684 KB

In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations.