Automated placement and routing
โ Scribed by A.D. Brown
- Publisher
- Elsevier Science
- Year
- 1988
- Tongue
- English
- Weight
- 510 KB
- Volume
- 20
- Category
- Article
- ISSN
- 0010-4485
No coin nor oath required. For personal study only.
โฆ Synopsis
The field of microelectronics continues to expand at an amazing rate. Starting at about 1963, the number of active devices that semiconductor technologists can pack onto a single chip has approximately doubled each year. Only recently (in the last few years) has the rate of increase started to decline slightly.
The problems facing the computer scientist involved in providing CAD support tools are severe. Semiconductor technology capability rises exponentially, and the problems associated with automated layout, design and verification of these circuits is increasing factorially. The principal problem is that no formal algorithms exist to solve these problems rigorously.
The way things were and the way they are going
The problems confronting a chip designer are similar to those of a town planner. Each has a set of modules (arithmetic logic units, read-only memory, random access memory, multiplexers, housing units, shopping centres, administrative buildings and so on) that has to be wired up according to some predefined pattern. (One has a connectivity netlist, the other constraints of local planning regulations and common sense -there is no point in putting a shopping centre in an area where there is access only by a mud track and there is nowhere to park.)
The differences are in the scale of the problem 1 . In the early 1960s, when planar technology was in its infancy, the only difference was that a road was 20 metres wide, and an aluminium track was maybe 50 microns. Apart from a scale factor of about 4.10 s, the problems of laying out a chip about I mm on a side were of comparable complexity to organizing an urban area about a mile on a side -not trivial, but certainly tractable by an experienced professional.
The big problem was that as chip geometry went down in size, die size went up, with the result that the size of the dataset confronting the chip designer increased explosively. To put things in perspective, laying out a 'typical' VLSl chip these days -chip 10 mm on a side, lambda down to 0.2/~ -is equivalent to a town planner trying to design a town equal in area to the entire landmass of western Europe, all at urban street densities.
Clearly, this problem is not tractable in a sensible time-
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