Asynchronous System-on-Chip Interconnect

✍ Scribed by Dr John Bainbridge (auth.)

• Publisher: Springer-Verlag London
• Year: 2002
• Tongue: English
• Leaves: 150
• Series: Distinguished Dissertations
• Edition: 1
• Category: Library

✦ Synopsis

Asynchronous System-on-Chip Interconnect describes the use of an entirely asynchronous system-bus for the modular construction of integrated circuits. Industry is just awakening to the benefits of asynchronous design in avoiding the problems of clock-skew and multiple clock-domains, an din parallel with this is coming to grips with Intellectual Property (IP) based design flows which emphasise the need for a flexible interconnect strategy. In this book, John Bainbridge investigates the design of an asynchronous on-chip interconnect, looking at all the stages of the design from the choice of wiring layout, through asynchronous signalling protocols to the higher level problems involved in supporting split transactions. The MARBLE bus (the first asynchronous SoC bus) used in a commercial demonstrator chip containing a mixture of asynchronous and synchronous macrocells is used as a concrete example throughout the book.

✦ Table of Contents

Front Matter....Pages i-xvii
Introduction....Pages 1-7
Asynchronous Design....Pages 9-21
System Level Interconnect Principles....Pages 23-30
The Physical (Wire) Layer....Pages 31-40
The Link Layer....Pages 41-59
Protocol Layer....Pages 61-70
Transaction Layer....Pages 71-81
MARBLE: A Dual-Channel Split Transfer Bus....Pages 83-100
Evaluation....Pages 101-114
Conclusion....Pages 115-122
Back Matter....Pages 123-139

✦ Subjects

Control Structures and Microprogramming