𝔖 Bobbio Scriptorium
✦   LIBER   ✦

Area-time associated test cost model for SoC and lower bound of test time

✍ Scribed by Jin-yi Zhang; Han-yi Weng; Xu-hui Huang; Wan-lin Cai

Book ID
107482844
Publisher
Chinese Electronic Periodical Services
Year
2011
Tongue
English
Weight
409 KB
Volume
15
Category
Article
ISSN
1007-6417

No coin nor oath required. For personal study only.

πŸ“œ SIMILAR VOLUMES

Test cost reduction for logic circuits:
Test cost reduction for logic circuits: Reduction of test data volume and test application time
✍ Yoshinobu Higami; Seiji Kajihara; Hideyuki Ichihara; Yuzo Takamatsu πŸ“‚ Article πŸ“… 2005 πŸ› John Wiley and Sons 🌐 English βš– 347 KB

## Abstract We believe that reduction of the testing cost is becoming increasingly important as the size of VLSIs becomes larger. Moreover, as the structure of VLSIs becomes more complicated, test compaction, test compression, and test application time reduction for non‐stuck‐at faults, such as del