In this article, an algorithm able to deal at the same time with wire frame and surface patch models for the method of moments in time domain is presented. After a unified theory combining both models, attention is focused on stability dependence issues on the time basis function chosen and on other
Analysis of the design space available for high-kgate dielectrics in nanoscale MOSFETs
โ Scribed by David J Frank; Hon-Sum P Wong
- Publisher
- Elsevier Science
- Year
- 2000
- Tongue
- English
- Weight
- 593 KB
- Volume
- 28
- Category
- Article
- ISSN
- 0749-6036
No coin nor oath required. For personal study only.
โฆ Synopsis
We present an analysis of the scaling behavior of MOSFETs with high-k gate insulators which elucidates the useful design space for such insulators. This analysis demonstrates that the design space is smaller than might be hoped and that within it, nanoscale bulk MOSFETs can only gain up to โผ20% additional scaling by use of high-k insulators, while symmetric double-gated FETs may gain up to โผ30%. It is shown that this analysis does not depend significantly on the gate sidewall dielectric constant or its spacing.
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