✦ LIBER ✦

Analysing trade-offs in scan power and test data compression for systems-on-a-chip

✍ Scribed by Rosinger, P.M.; Gonciari, P.T.; Al-Hashimi, B.M.; Nicolici, N.

Book ID: 114448517
Publisher: The Institution of Electrical Engineers
Year: 2002
Tongue: English
Weight: 342 KB
Volume: 149
Category: Article
ISSN: 1350-2387
DOI: 10.1049/ip-cdt:20020450

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

[IEEE 2007 Ph.D Research in Microelectro

[IEEE 2007 Ph.D Research in Microelectronics and Electronics Conference - (2007.07.2-2007.07.5)] 2007 Ph.D Research in Microelectronics and Electronics Conference - Systems-on-chip: Use of test data compression technique for reducing test time

✍ Dalmasso, Julien; Flottes, Marie-Lise; Rouzeyre, Bruno 📂 Article 📅 2007 🏛 IEEE ⚖ 563 KB

[IEEE Computer Soc Proceedings. 18th Int

[IEEE Computer Soc Proceedings. 18th International Conference on VLSI Design - Kolkata, India (3-7 Jan. 2005)] 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design - Heterogeneous and multi-level compression techniques for test volume reduction in systems-on-chip

✍ Lingapan, L.; Ravi, S.; Raghunathan, A.; Jha, N.K.; Chakradhar, S.T. 📂 Article 📅 2005 🏛 IEEE Computer Soc 🌐 English ⚖ 256 KB

A January 2005 conference fostered interaction between the domains of system architecture, logic and circuit design, and device fabrication. Design automation, embedded systems design, rapid prototyping, and embedded software design were some other themes. Papers from the conference focus on power-a