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An architecture for high-performance/small-area multipliers for use in digital filtering applications

โœ Scribed by Kwentus, A.Y.; Hing-Tsun Hung; Willson, A.N., Jr.

Book ID
119773931
Publisher
IEEE
Year
1994
Tongue
English
Weight
649 KB
Volume
29
Category
Article
ISSN
0018-9200

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A low power dissipation architecture of
A low power dissipation architecture of high-performance multiprocessor for state-space digital filters using block-state realization
โœ Yoshitaka Tsunekawa; Michiru Iwawaki; Mamoru Miura ๐Ÿ“‚ Article ๐Ÿ“… 2000 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 322 KB ๐Ÿ‘ 2 views

In this paper, a low power dissipation architecture of high-performance multiprocessor is proposed for statespace digital filters using block-state realization in order to realize high-accuracy, high-speed process with reduced hardware previously proposed by the authors. Distributed arithmetic is ap