<p>Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releas
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
β Scribed by Donald E. Thomas, Elizabeth D. Lagnese, Robert A. Walker, Jayanth V. Rajan, Robert L. Blackburn, John A. Nestor
- Publisher
- Springer
- Year
- 1989
- Tongue
- English
- Leaves
- 315
- Series
- The Springer International Series in Engineering and Computer Science
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
π SIMILAR VOLUMES
<p>A critical step in the design of a DSP system is to identify for each of its components (DSP kernels) an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. The book covers the entire solution space comprising
Standard syntax and semantics for VerilogR HDL-based RTL synthesis are described in this standard.
A standard syntax and semantics for VHDL register transfer level (RTL) synthesis is defined. The subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis is defined, along with the semantics of that subset for the synthesis domain.
<p><em>System-Level Synthesis</em> deals with the concurrent design of electronic applications, including both hardware and software. The issue has become the bottleneck in the design of electronic systems, including both hardware and software, in several major industrial fields, including telecommu
<p><em>System-Level Synthesis</em> deals with the concurrent design of electronic applications, including both hardware and software. The issue has become the bottleneck in the design of electronic systems, including both hardware and software, in several major industrial fields, including telecommu