[ACM Press the 20th symposium - Providence, Rhode Island, USA (2010.05.16-2010.05.18)] Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10 - Graphene tunneling FET and its applications in low-power circuit design

✍ Scribed by Yang, Xuebei; Chauhan, Jyotsna; Guo, Jing; Mohanram, Kartik

• Book ID: 127249388
• Publisher: ACM Press
• Year: 2010
• Weight: 542 KB
• Category: Article
• ISBN: 145030012X
• DOI: 10.1145/1785481.1785544

✦ Synopsis

Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high I on/Ioff, and potential for large scale processing and fabrication. This paper combines atomistic quantum transport modeling with circuit simulation to explore GNR TFET circuits for low-power applications. A quantitative study of the effects of variations on the performance and reliability of GNR TFET circuits is also presented. Simulation results indicate that GNR TFET circuits are extremely competitive in performance in comparison to conventional CMOS circuits at comparable operating points, with static power consumption that is lower by 8-9 orders of magnitude. It is also observed that GNR TFET circuits are susceptible to parameter variations, motivating engineering and design challenges to be addressed by the device and CAD communities.