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A VLSI implementation of residue adders

✍ Scribed by Bayoumi, M.; Jullien, G.; Miller, W.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

VLSI implementation of a 5-trit full add

✍ Mouftah, H.T.; Garba, A.I. 📂 Article 📅 1984 🏛 The Institution of Electrical Engineers ⚖ 699 KB

Erratum: VLSI implementation of a 5-trit

✍ Mouftah, H.T. 📂 Article 📅 1986 🏛 The Institution of Electrical Engineers ⚖ 75 KB

A fast VLSI adder architecture

✍ Srinivas, H.R.; Parhi, K.K. 📂 Article 📅 1992 🏛 IEEE 🌐 English ⚖ 495 KB

The complexity of a VLSI adder

✍ Robert B. Johnson Jr. 📂 Article 📅 1980 🏛 Elsevier Science 🌐 English ⚖ 234 KB

Lower bounds for VLSI implementation of

✍ Magdy A. Bayoumi 📂 Article 📅 1986 🏛 Elsevier Science 🌐 English ⚖ 593 KB

A VLSI architecture for RNS with MI adde

✍ Ferruccio Barsi; Enrico Martinelli 📂 Article 📅 1991 🏛 Elsevier Science 🌐 English ⚖ 718 KB