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A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC

✍ Scribed by Toyokura, M.; Kodama, H.; Miyagoshi, E.; Okamoto, K.; Gion, M.; Minemaru, T.; Ohtani, A.; Araki, T.; Takeno, H.; Akiyama, T.; Wilson, B.; Aono, K.

Book ID: 119774193
Publisher: IEEE
Year: 1994
Tongue: English
Weight: 662 KB
Volume: 29
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.340420

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high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 Am dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in re