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A three-dimensional CMOS design methodology

โœ Scribed by Hoefflinger, B.; Liu, S.T.; Vajdic, B.


Book ID
119798302
Publisher
IEEE
Year
1984
Tongue
English
Weight
403 KB
Volume
19
Category
Article
ISSN
0018-9200

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Design methodology for full custom CMOS
โœ C. Piguet ๐Ÿ“‚ Article ๐Ÿ“… 1983 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 910 KB

A highly structured design methodology is necessary to be successful in the design of VLSI integrated circuits with more than 100000 transistors on a chip. Such a methodology is described: it is based on the regularity of the circuit architecture with an associated chip floor plan and on a new layou