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A Task-Centric Memory Model for Scalable Accelerator Architectures

โœ Scribed by Kelm, J.H.; Johnson, D.R.; Lumetta, S.S.; Patel, S.J.; Frank, M.I.

Book ID
114583240
Publisher
IEEE
Year
2010
Tongue
English
Weight
691 KB
Volume
30
Category
Article
ISSN
0272-1732

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One of the major limitations of distributed memory systems (DMSs) is the high cost for interprocessor communication, which can be minimized by having an efficient task partitioning and scheduling algorithm. It is well known that scheduling the tasks of a directed acyclic graph (DAG) to obtain an opt