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A surface-potential-based high-voltage compact LDMOS transistor model

✍ Scribed by Aarts, A.; D'Halleweyn, N.; van Langevelde, R.


Book ID
114617787
Publisher
IEEE
Year
2005
Tongue
English
Weight
476 KB
Volume
52
Category
Article
ISSN
0018-9383

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## Abstract The heat generation process inside thin‐film silicon‐on‐insulator LDMOS structures accounting for Linear Doping Profile (LDP) or Variation on Lateral Doping (VLD) is analysed in this paper by means of numerical simulation tools and analytical modeling. A uniform heat density, mainly due