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A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses

โœ Scribed by Arima, Y.; Murasaki, M.; Yamada, T.; Maeda, A.; Shinohara, H.


Book ID
119773707
Publisher
IEEE
Year
1992
Tongue
English
Weight
719 KB
Volume
27
Category
Article
ISSN
0018-9200

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A reconfigurable analog VLSI neural netw
โœ Bo, G. M.; Caviglia, D. D.; Valle, M.; Stratta, R.; Trucco, E. ๐Ÿ“‚ Article ๐Ÿ“… 1998 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 111 KB ๐Ÿ‘ 1 views

In this paper a reconfigurable analog VLSI neural network architecture is presented. The analog architecture implements a Multi-Layer Perceptron whose topology can be programmed without any modification of the off-chip connections. The architecture is scaleable and modular since it is based on a sin