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A reconfigurable analog VLSI neural network architecture with non-linear synapses

✍ Scribed by Bo, G. M.; Caviglia, D. D.; Valle, M.; Stratta, R.; Trucco, E.

Publisher: John Wiley and Sons
Year: 1998
Tongue: English
Weight: 111 KB
Volume: 26
Category: Article
ISSN: 0098-9886
DOI: 10.1002/(sici)1097-007x(199805/06)26:3<307::aid-cta14>3.0.co;2-5

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✦ Synopsis

In this paper a reconfigurable analog VLSI neural network architecture is presented. The analog architecture implements a Multi-Layer Perceptron whose topology can be programmed without any modification of the off-chip connections. The architecture is scaleable and modular since it is based on a single-chip configurable basic module. To obtain a robust behaviour with respect to noise and errors introduced in the computation by analog circuits, we use non-linear synapses and linear neurons as neural primitives.

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