A reconfigurable bus structure for multiprocessors with bandwidth reuse

✍ Scribed by Sibabrata Ray; Hong Jiang

• Publisher: Elsevier Science
• Year: 1999
• Tongue: English
• Weight: 331 KB
• Volume: 45
• Category: Article
• ISSN: 1383-7621
• DOI: 10.1016/s1383-7621(98)00025-3

✦ Synopsis

Shared bus is one of the most popular communication media for tightly coupled multiprocessing environments. However, a shared bus can provide only limited bandwidth, a fact that limits its usability. In this paper we propose a re-con®gurable bus structure with both temporal and spatial/spectral bandwidth expansion and describe a method for reusing part of the bandwidth available from temporal and spatial/spectral bandwidth expansion without introducing any buering delay. Two polynomial time algorithms are developed to optimally recon®gure the bus under the design constraints for a given trac pattern. For one algorithm the architecture is geared to obtain low average system response time. The other algorithm minimizes the system response time on a dierent architecture that is designed to reduce the disparity of response time among dierent nodes. We have compared the performance of recon®gured buses with that of the traditional slotted buses for uniform and localized trac patterns and found that the recon®gured bus outperforms the traditional slotted bus substantially in most practical scenarios.