๐”– Bobbio Scriptorium
โœฆ   LIBER   โœฆ

A prolog implementation of an instruction-level processor simulator

โœ Scribed by Ariel Pashtan


Book ID
112210375
Publisher
John Wiley and Sons
Year
1987
Tongue
English
Weight
559 KB
Volume
17
Category
Article
ISSN
0038-0644

No coin nor oath required. For personal study only.


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In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations.