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A pipelined interface for high floating-point performance with precise exceptions

✍ Scribed by Iacobovici, S.


Book ID
117878308
Publisher
IEEE
Year
1988
Tongue
English
Weight
773 KB
Volume
8
Category
Article
ISSN
0272-1732

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A High-Performance Architecture with a M
✍ JosΓ© M. FernΓ‘ndez; FΓ©lix Moreno; Juan M. Meneses πŸ“‚ Article πŸ“… 1996 πŸ› Elsevier Science 🌐 English βš– 90 KB

high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 Am dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in re