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A low-power 16×16-b parallel multiplier utilizing pass-transistor logic

✍ Scribed by Law, C.F.; Rofail, S.S.; Yeo, K.S.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A 3.8-ns CMOS 16×16-b multiplier using c

✍ Yano, K.; Yamanaka, T.; Nishida, T.; Saito, M.; Shimohigashi, K.; Shimizu, A. 📂 Article 📅 1990 🏛 IEEE 🌐 English ⚖ 650 KB