๐”– Bobbio Scriptorium
โœฆ   LIBER   โœฆ

A Low-Jitter Synchronous Clock Distribution Scheme Using a DAC Based PLL

โœ Scribed by Wu, Jie; Ma, Yichao; Zhang, Jie; Xie, Mingpu

Book ID
111655800
Publisher
IEEE
Year
2010
Tongue
English
Weight
548 KB
Volume
57
Category
Article
ISSN
0018-9499

No coin nor oath required. For personal study only.

๐Ÿ“œ SIMILAR VOLUMES

[IEEE 1997 IEEE International Solids-Sta
[IEEE 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (6-8 Feb. 1997)] 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers - A 0.35 ฮผm CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors
โœ Young, I.A.; Mar, M.F.; Bhushan, B. ๐Ÿ“‚ Article ๐Ÿ“… 1997 ๐Ÿ› IEEE ๐ŸŒ English โš– 486 KB