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A dividing ratio changeable digital PLL with low jitter using a multiphase clock divider

✍ Scribed by Kuniaki Fujimoto; Mitsutoshi Yahara; Hirofumi Sasaki

Book ID: 102819262
Publisher: Wiley (John Wiley & Sons)
Year: 2011
Tongue: English
Weight: 751 KB
Volume: 94
Category: Article
ISSN: 1942-9533
DOI: 10.1002/ecj.10340

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