A latch-up-free CMOS RAM cell with well-source structure: M Yoshimoto, K Anami, K Watabe, T Yoshihara, Snagao, Y Akasaka (Mitsubishi Electr. Corp., Hyogo, Japan) IEEE J. Solid-State Circuits (USA) vol. SC-22, no. 4, pp. 538–542 (Aug. 1987)

• Book ID: 104157729
• Publisher: Elsevier Science
• Year: 1988
• Tongue: English
• Weight: 95 KB
• Volume: 19
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/s0026-2692(88)80197-6