Abstract
This paper discusses the test‐generation circuit which automatically generates a test pattern for a combinational circuit. The test‐generation circuit is designed so that two algorithms of automatic test generation and fault simulation can be executed by the circuit. The test pattern for the circuit under test is generated at a high speed by simulating the operation of the test‐generation circuit using the dedicated logic simulation machine SP. As a result of performance evaluation for the well known benchmark circuits, the test‐generation circuit was constructed with eleven times the number of SP elements on the average compared with the circuit under test. By a simulation using only one SP processor, the operation of the test‐generation circuit could be simulated at 6 kHz on the average. Thus, it is seen that the test pattern for the circuit under test can be generated with a high fault coverage with a speed surpassing the software on a large‐scale computer. The method proposed herein is to apply effectively the architecture of the dedicated machine for a high‐speed logic simulation to the search problem such as test generation. Thus, the validity of the idea was verified.