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A High-Performance Low Cost SAD Architecture for Video Coding

✍ Scribed by Yufei, L.; Feng Xiubo; Wang Qin


Book ID
117910197
Publisher
IEEE
Year
2007
Tongue
English
Weight
476 KB
Volume
53
Category
Article
ISSN
0098-3063

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high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 Am dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in re