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A High-Level Power Model for MPSoC on FPGA

โœ Scribed by Piscitelli, R.; Pimentel, A.


Book ID
114572154
Publisher
IEEE
Year
2012
Tongue
English
Weight
268 KB
Volume
11
Category
Article
ISSN
1556-6056

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This paper presents a high level power estimation methodology for a Network-on-Chip (NoC) router, that is capable of providing cycle accurate power profile to enable power exploration at system level. Our power macro model is based on the number of flits passing through a router as the unit of abstr