A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations

✍ Scribed by Sridharan, K.; Priya, T.K.

• Book ID: 119817452
• Publisher: IEEE
• Year: 2007
• Tongue: English
• Weight: 191 KB
• Volume: 54
• Category: Article
• ISSN: 1932-4529
• DOI: 10.1109/tie.2007.894726