A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation

✍ Scribed by Man Lung Mui; Banerjee, K.; Mehrotra, A.

• Book ID: 114617285
• Publisher: IEEE
• Year: 2004
• Tongue: English
• Weight: 266 KB
• Volume: 51
• Category: Article
• ISSN: 0018-9383
• DOI: 10.1109/ted.2003.820651