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A fast-lock delay-locked loop architecture with improved precharged PFD

โœ Scribed by Soh Lip-Kai; Mohd-Shahiman Sulaiman; Zubaida Yusoff


Book ID
106342451
Publisher
Springer
Year
2008
Tongue
English
Weight
364 KB
Volume
55
Category
Article
ISSN
0925-1030

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A 120โ€“420 MHz delay-locked loop with mul
โœ Ko-Chi Kuo; Yi-Hsi Hsu ๐Ÿ“‚ Article ๐Ÿ“… 2010 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 589 KB

A low-jitter and low-power dissipation delay-locked loop (DLL) is presented. A proposed multi-band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity.