In the conventional Β―oating point multipliers, the rounding stage is usually constructed by using a high speed adder for the increment operation, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it may accompany additional execution time and hardware comp
A dual precision IEEE floating-point multiplier
β Scribed by Guy Even; Silvia M. Mueller; Peter-Michael Seidel
- Publisher
- Elsevier Science
- Year
- 2000
- Tongue
- English
- Weight
- 306 KB
- Volume
- 29
- Category
- Article
- ISSN
- 0167-9260
No coin nor oath required. For personal study only.
β¦ Synopsis
A new algorithm for computing IEEE-compliant rounding is presented, called injection-based rounding. Injection-based rounding is simple and facilitates using the same rounding circuitry for di!erent precisions. We demonstrate the usefulness of injection-based rounding in a design of an IEEE #oating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. The multiplier is designed to minimize hardware cost by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions. The latency of the multiplier is in single-precision two clock cycles and in double precision the latency is three clock cycles, where each pipeline stage contains roughly 15 logic levels.
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