A floating point multiplier performing IEEE rounding and addition in parallel
✍ Scribed by Woo-Chan Park; Tack-Don Han; Shin-Dug Kim; Sung-Bong Yang
- Publisher
- Elsevier Science
- Year
- 1999
- Tongue
- English
- Weight
- 236 KB
- Volume
- 45
- Category
- Article
- ISSN
- 1383-7621
No coin nor oath required. For personal study only.
✦ Synopsis
In the conventional ¯oating point multipliers, the rounding stage is usually constructed by using a high speed adder for the increment operation, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it may accompany additional execution time and hardware components for renormalization which may occur by an over¯ow from the rounding operation. A ¯oating-point multiplier performing addition and IEEE rounding in parallel is designed by optimizing the operational ¯ow based on the characteristics of ¯oating point multiplication operation. A hardware model for the ¯oating point multiplier is proposed and its operational model is algebraically analyzed in this research. The ¯oating point multiplier proposed does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-eective design can be achieved by this approach.