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A 5-ns 32 K ×8/×9 bi-CMOS TTL SRAM with alternated bit line load architecture

✍ Scribed by Shigeki Ohbayashi; Toru Shiomi; Ryuichi Matsuo; Tadashi Sumi; Hiroki Honda; Yoshiyuki Ishigaki; Kimiharu Uga; Masahiro Ishida; Yoshio Kohno

Book ID: 112078862
Publisher: John Wiley and Sons
Year: 1994
Tongue: English
Weight: 843 KB
Volume: 77
Category: Article
ISSN: 8756-663X
DOI: 10.1002/ecjb.4420770208

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✍ Shiomi, T.; Wada, T.; Ohbayashi, S.; Ohba, A.; Honda, H.; Ishigaki, Y.; Hine, S. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 718 KB