✦ LIBER ✦

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

✍ Scribed by Nosaka, H.; Sano, E.; Ishii, K.; Ida, M.; Kurishima, K.; Yamahata, S.; Shibata, T.; Fukuyama, H.; Yoneyama, M.; Enoki, T.; Muraguchi, M.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A 10-Gb/s CMOS clock and data recovery c

✍ Savoj, J.; Razavi, B. 📂 Article 📅 2001 🏛 IEEE 🌐 English ⚖ 216 KB

A 10-Gb/s CMOS clock and data recovery c

✍ Savoj, J.; Razavi, B. 📂 Article 📅 2003 🏛 IEEE 🌐 English ⚖ 569 KB

A 1–16-Gb/s Wide-Range Clock/Data Recove

✍ Chang-Lin Hsieh; Shen-Iuan Liu 📂 Article 📅 2011 🏛 Institute of Electrical and Electronics Engineers 🌐 English ⚖ 495 KB

[IEEE IEEE 2005 Custom Integrated Circui

✍ Jing-Hong Conan Zhan, ; Duster, J.S.; Kornegay, K.T. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 436 KB

[IEEE ESSCIRC 2004 - 29th European Solid

✍ Rezayee, A.; Martin, K. 📂 Article 📅 2003 🏛 IEEE 🌐 English ⚖ 303 KB

[IEEE 1993 IEEE International Solid-Stat

✍ Banu, M.; Dunlop, A. 📂 Article 📅 1993 🏛 IEEE ⚖ 356 KB