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A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller

โœ Scribed by Gerosa, G.; Alexander, M.; Alvarez, J.; Croxton, C.; D'Addeo, M.; Kennedy, A.R.; Nicoletta, C.; Nissen, J.P.; Philip, R.; Reed, P.; Sanchez, H.; Taylor, S.A.; Burgess, B.


Book ID
119774926
Publisher
IEEE
Year
1997
Tongue
English
Weight
373 KB
Volume
32
Category
Article
ISSN
0018-9200

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A 32 b microprocessor with on-chip 2 K b
๐Ÿ“‚ Article ๐Ÿ“… 1988 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 98 KB

tained on an 8.4 โ€ข 8.4 mm 2 die. The circuit has been designed for an operating frequency of 30 MHz under worst-case conditions. Architectural features include 32-32-b general-purpose registers, 48 or 64-b virtual addressing, and multiprocessor capability, including semaphore instructions and suppor