A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

✍ Scribed by Jakub Kedzierski; Peiqi Xuan; Vivek Subramanian; Jeffrey Bokor; Tsu-Jae King; Chenming Hu; Erik Anderson

• Book ID: 102976888
• Publisher: Elsevier Science
• Year: 2000
• Tongue: English
• Weight: 635 KB
• Volume: 28
• Category: Article
• ISSN: 0749-6036
• DOI: 10.1006/spmi.2000.0947

✦ Synopsis

As the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 µA µm -1 on-current and on/off current ratios of 10 6 , for a conservative oxide thickness of 40 Å and |V g -V t | = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in |V t | is obtained in devices with gate lengths ranging from 100 to 20 nm.