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A 1.8 V 15-bit 1 mW 2nd-Order Sigma-Delta Modulator

✍ Scribed by Wei Yang; C. Andre T. Salama

Book ID
110261639
Publisher
Springer
Year
2001
Tongue
English
Weight
186 KB
Volume
26
Category
Article
ISSN
0925-1030

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This paper uses a CAD methodology proposed by the authors to design a low-power second-order M. This modulator has been fabricated in a 0•7 m CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16•4 bit at a digital output rate of 9•6 kHz with a power con