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A 16-bit 250-kHz delta-sigma modulator and decimation filter

✍ Scribed by Maulik, P.C.; Chadha, M.S.; Lee, W.L.; Crawley, P.J.


Book ID
115536369
Publisher
IEEE
Year
2000
Tongue
English
Weight
574 KB
Volume
35
Category
Article
ISSN
0018-9200

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This paper uses a CAD methodology proposed by the authors to design a low-power second-order M. This modulator has been fabricated in a 0•7 m CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16•4 bit at a digital output rate of 9•6 kHz with a power con