A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors

✍ Scribed by Okamura, H.; Toyoshima, H.; Takeda, K.; Oguri, T.; Nakamura, S.; Takada, M.; Imai, K.; Kinoshita, Y.; Yoshida, H.; Yamazaki, T.

• Book ID: 119774430
• Publisher: IEEE
• Year: 1995
• Tongue: English
• Weight: 959 KB
• Volume: 30
• Category: Article
• ISSN: 0018-9200
• DOI: 10.1109/4.475707